Static Timing Analysis | STA Engineer | Setup Time and Hold Time

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In this video, we will explore about a new area discussed in VLSI Engineering video that is Static Timing Analysis in short STA. After physical design, we need Physical Verification to assure if the layout is proper. Physical Verification is a crucial part in Backend Design Flow which includes DRC (Design Rule Checks), LVS (Layout Vs Schematic) ame STA (Static Timing Analysis). We will start with basic difference between Dynamic Timing Analysis and Static Timing Analysis. After that we will see the basic definition and concept of setup time and hold time. We will also derive an expression for condition to meet both setup and hold time. We will also see in what conditions we have setup and hold violations. After that we will see how to prepare for a Physical Design Job? What topics should be studied? Then, we have listed few companies like Intel, Qualcomm, NXP, Samsung etc which works in this PD or you can say VLSI domain. Then, we talked about the salaries offered to the freshers by these companies. Generally, big companies like MNCs, offer Rs 18-20 LPA package to freshers. At the end, I have provided you the name of three mentors who can help you or guide you to become a successful Physical Design Engineer.

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YouTube url:	https://youtu.be/zog8G11IbmA?list=PLXQ42cvQ8LuoBYyi_w0w4L9_VM_mpGhKb
Created:	1. 2. 2022 14:44:20

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Static Timing Analysis | STA Engineer | Setup Time and Hold Time